Ensure consistent spacing around colons in bit fields, operators,
statements and function calls.

Found by the linter (check-style).

Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd
Signed-off-by: Alexander Goncharov <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83281
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Eric Lai <[email protected]>
Reviewed-by: Subrata Banik <[email protected]>

The filename of the Elkhart Lake FSP binary changed in the FSP
repository. It's unlikely that it will be renamed to the original name
soon. Thus, update the filename in the coreboot repository.

Updating from commit id cc6399e:
2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP)

to commit id 800c857:
2024-06-25 15:47:28 +0800 - (Update Fsp.fd)

This brings in 23 new commits:
800c857 Update Fsp.fd
41e4590 NEX AZB IPU24.4 (5254_00) FSP
0efd8a3 IoT RPL-PS PV (5045_47) FSP
196e3fe Update README.md
380afd8 Update README.md
5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP
22762e9 Merge branch 'master' of https://github.com/intel/FSP
8134dbd Elkhart Lake IPU2024.3 FSP
3819544 add required SECURITY.md file for OSSF Scorecard compliance
a6ee963 Delete AlderLakeFspBinPkg.dec
9d819ea Deprecate Client/AlderLakeFspBinPkg
f963690 Raptor Lake FSP C.1.C8.50
f67f9ef Raptor Lake FSP C.0.C8.50
68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP
f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP
6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP
c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP
8cf0372 IoT ADL-N MR4 (5061_00)
e5ceb0b Merge branch 'master' of https://github.com/intel/FSP
aada6a5 Elkhart Lake IPU2024.2 FSP
90d1d3b Update README.md
1a5a3ee Testing
61c069a NEX RPL-S MR3 (4445_03) FSP

Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe
Signed-off-by: Felix Singer <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294
Reviewed-by: Werner Zeh <[email protected]>
Reviewed-by: Lean Sheng Tan <[email protected]>
Reviewed-by: Mario Scheithauer <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

Updating from commit id 09fcd218:
2024-02-23 06:42:12 +0000 - (Makefile: Test compiler for -Wincompatible-function-pointer-types)

to commit id b6f44e62:
2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10)

This brings in 58 new commits:
b6f44e62 futility: updater: Increase try count from 8 to 10
cfc87db2 OWNERS: Add czapiga
eabf5784 OWNERS: Remove twawrzynczak and quasisec
f8af818e host: Add stub implementation for pkcs11 key
aaf4ecbb crossystem: Add support for Panther Lake gpiochip
de89c5cd make_dev_ssd: allow ptracers to write proc/mem
ffc9cc15 utility: Add vbnv_util.py for debugging
b6174bdb futility: show: Print keyblock signature size and data size
6e39c99f Android: Add support for doing zipalign before doing apksigner
ead73381 futility: flash: Enhance WP status reporting by adding more instructions
c3368084 futility: modify private key validation to work for both local and cloud
c22d72f8 futility: flash: Correct the output syntax of 32bit hex
f423ae13 crossystem: Drop support for tried_fwb and fwb_tries
fc5488c7 futility: flash: Correct the allowlist of options
16dede85 Revert "futility: Split load_firmware_image() into two functions for AP and EC"
ded07831 futility: Try to load ecrw versions regardless of image type
7a685705 futility: Refactor code for --manifest
f5ad0856 futility: Add more checks for incompatible arguments
05659d33 futility/updater_manifest: Warn about inconsistent RW versions
6720827b futility: Support ecrw version for --manifest
daae7e56 futility: Split load_firmware_image() into two functions for AP and EC
40c77bba futility: Warn about inconsistent RW_FWID_A and RW_FWID_B versions
c168ac8e tests/futility/data: Update bios_geralt_cbfs.bin with swapped ecrw
512648ae host/lib: Add cbfstool_file_exists() and cbfstool_extract()
e37e6511 sign_official_build: add missing info keyword
2c0758b4 sign_official_build: loem support for firmware
016f6149 scripts/image_signing/swap_ec_rw: Always add ecrw.* as raw CBFS file
b26c700a scripts/image_signing/swap_ecrw: Support ecrw.version
2e8d1003 tlcl: Add const qualifier to TlclTakeOwnership arguments
96b8674c host: stop installing unused image signing scripts
8da83c43 Android: Handle update certs using for hardcoded certs
4ca60534 scripts/image_signing: Add swap_ec_rw
d30d6b54 make_dev_ssd: Remove logic choosing editor value
4cc5d090 futility/dump_fmap: Fix error message prefix for '-x'
e7062a58 futility/dump_fmap: Exit with error if specified section is not found
4489dd09 scripts: Remove newbitmaps directory
8dcc82b0 host/lib/cbfstool: Redesign cbfstool_get_config_value() API
856fd693 Android: Hack for now to let things silently fail instead of erroring
28845c97 sign_uefi: Handle case where the crdyshim key does not exist
201244c3 sign_uefi_unittest: Refactor in preparation for more tests
702f8b53 tests: Add tests for cbfstool_get_config_value()
52a21327 Android: Add support for gcloud KMS in android signing
3310c49f tests/futility/test_update.sh: Use unique test names for IFD tests
493f7afc sign_gsc_firmware: add support for Nightly target
5c307cad keycfg: more consistent typo fix
11e4f60b image_signing: Add missing arg in sign_uefi_kernel
37c730d8 keycfg: handle arrays appropriately in key_config
59c37697 sign_uefi: Add detached crdyboot signature
b66926e2 sign_uefi: Refactor the is-pkcs11 function for reuse
94aa8b80 image_signing: Pass crdyshim private key to sign_uefi.py
0ac99bcb sign_uefi: Stop signing crdyboot files with sbsign
6f6a6432 vboot_reference-sys: replace denylist with allowlist
73ebd8f8 vboot_reference-sys: add vboot_host pkg-config fallback
476282ef make_dev_ssd: Skip firmware validity checks on nonchrome
9330a65a vboot_reference: Add support for allowing overlayfs
48c8833f sign_official_build: remove cloud-signing
aa70bb19 create_new_keys.sh: add --arv-root-uri
38d1af69 sign_official_build: Dedup calls to sign_uefi.py

Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533
Signed-off-by: Felix Singer <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83295
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Lean Sheng Tan <[email protected]>

This port was done via autoport and subsequent manual tweaking.
Special thanks to Nicholas Chin! This port would have never succeeded
without his help.

The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection switch and onboard Power and Reset switches.

Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- USB 2.0 Ports
- Vertical Type A USB 2.0
- USB 3.1 Gen1 Ports
- HD Audio Jack (audio output)
- Front panel audio connector (audio output)
- RJ-45 Gigabit LAN Port
- SATA3 6.0 Gb/s connectors
- mSATA/mini-PCI Express slot
- half mini-PCI Express slot
- PCI Express 3.0 x16 slots (both)
- PCI Express 2.0 x4 slot
- PCI Express 2.0 x1 slot

Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection Switch
- Slow Mode Switch (locks the CPU at 800MHz)

not (yet) tested:
- IR header
- COM Port header
- Power LED header
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- Optical SPDIF Out Port

not (yet) working:
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
- Post Status Checker (PSC)

Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746
Signed-off-by: Jan Philipp Groß <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Nicholas Chin <[email protected]>
Reviewed-by: Felix Singer <[email protected]>

This double-colon target doesn't do anything unless it's implemented by
another makefile. It's intended to be used only by the site-local
makefile to allow it to run any necessary steps before the actual
coreboot build begins.

Signed-off-by: Martin Roth <[email protected]>
Change-Id: I01f98c9cf8375bca21ab87f9becf66a25402c758
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83198
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Matt DeVillier <[email protected]>
Reviewed-by: Felix Held <[email protected]>

Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50
Signed-off-by: Elyes Haouas <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Lean Sheng Tan <[email protected]>

This reverts commit 6ab188e.

This breaks the build using a slightly older toolchain that doesn't know
this option yet.

Signed-off-by: Felix Held <[email protected]>
Change-Id: I0bdc909c0e53b5353743dca521c963bbec792f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83311
Reviewed-by: Felix Singer <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Elyes Haouas <[email protected]>
Reviewed-by: Nicholas Chin <[email protected]>

Refactor CSE lite configs (specifically CSE sync related) to support
the alternative of sending CSE communication from the payload.

When the SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE sync operations and rely on the payload CSE
driver implementation.

The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_LITE_PSR
- SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
- SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE
- SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: I5ddaf6e29949231db84b14bf7ea2d34866bb8e6c
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83228
Reviewed-by: Eric Lai <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Dinesh Gehlot <[email protected]>
Reviewed-by: Nick Vaccaro <[email protected]>

Refactor CSE lite End-of-Post (EOP) configs to support
the alternative of sending CSE communication from the payload.

When the SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config is selected, coreboot
will skip initiating CSE EOP operations and rely on the payload CSE
driver implementation.

The following configs are modified to ensure coreboot skips CSE
communication when SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is enabled:
- SOC_INTEL_CSE_SEND_EOP_EARLY
- SOC_INTEL_CSE_SEND_EOP_LATE
- SOC_INTEL_CSE_SEND_EOP_ASYNC
- SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: Ia6b616163d02be8d637b134fd3728c391fc63c90
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83229
Reviewed-by: Dinesh Gehlot <[email protected]>
Reviewed-by: Nick Vaccaro <[email protected]>
Reviewed-by: Eric Lai <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

This patch skips the CSE firmware version print when CSE sync is done
by payload. The payload is responsible to dump the CSE version.

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: I1a9e5583c79ebd81291a4b3ae24529b4582502cb
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83230
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Dinesh Gehlot <[email protected]>
Reviewed-by: Nick Vaccaro <[email protected]>
Reviewed-by: Eric Lai <[email protected]>

This patch skips the ISH firmware version print when CSE sync is done
by payload. The payload is responsible to dump the ISH version as
ISH version resides into the CSE boot partition table.

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: I1895a4d3c44838a9cc6380912f09aa4f0e6687bd
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83231
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Nick Vaccaro <[email protected]>
Reviewed-by: Dinesh Gehlot <[email protected]>
Reviewed-by: Eric Lai <[email protected]>

This patch disables the ME status reporting functionality
(dump_me_status, print_me_fw_version) in the CSE driver when
SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD is defined.

This is likely intended for platforms or configurations where the
CSE communication is only limited to payload.

BUG=b:305898363
TEST=Able to build google/rex.

Change-Id: I5e360408a7847968117df475ff244d79ceafa23f
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83233
Reviewed-by: Nick Vaccaro <[email protected]>
Reviewed-by: Dinesh Gehlot <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Eric Lai <[email protected]>

This change modifies the get_me_fw_version() function to be statically
scoped within src/soc/intel/common/block/cse/cse.c, as it is only used
by the print_me_fw_version() function in the same file.

The function declaration is also removed from intelblocks/cse.h.

The order of the function definitions in cse.c was also changed to be
more logical, with the now static helper function get_me_fw_version()
defined first, before it is used.

TEST=Able to build google/rex.

Change-Id: Idd3a6431cfa824227361c7ed4f0d5300f1d04846
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83257
Reviewed-by: Dinesh Gehlot <[email protected]>
Reviewed-by: Nick Vaccaro <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

This change skips the ME firmware version logging in
print_me_fw_version() if the ME firmware SKU is detected as Lite SKU.

The reasoning is that the RO (BP1) and RW (BP2) versions are already
logged by the cse_print_boot_partition_info() function for Lite SKUs,
making the additional log redundant.

The check for the Lite SKU has been moved to print_me_fw_version(),
where the decision to print the version is made, instead of in
get_me_fw_version(), where the version information is retrieved.

TEST=Able to build and boot google/rex.

w/o this patch:

[DEBUG]  ME: Version: Unavailable

w/ this patch:

Unable to see such debug msg.

Change-Id: Ic3843109326153d5060c2c4c25936aaa6b4cddda
Signed-off-by: Subrata Banik <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83258
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Dinesh Gehlot <[email protected]>

Working:
 - Both DIMM slots
 - All Rear USB 2.0 ports
 - Integrated graphics (libgfxinit)
 - Realtek RTL8111F GbE
 - Flashing internally with flashrom (Note: Works from stock too
        due to Gigabyte not following Intel recommendations,
        confusing ME)
 - SeaBIOS (1.16.3) to boot Arch Linux Installer
 - EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
 - Audio output (green jack, rear)
 - S3 suspend/resume
 - VBT

Untested for now (i.e. should work, will eventually test):
 - EHCI debug
 - Front USB 2.0 ports
 - The other audio jacks
 - PCIe ports
 - Non-Linux OSes

Untestable (i.e. cannot test due to unavailable hardware):
 - PS/2 port
 - Serial port
 - SATA ports

Not working:
 - USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
   so its firmware needs to be loaded on each boot. However,
   documentation about the (chip-specific) firmware loading procedure
   is nowhere to be found.
 - Super I/O automatic fan control: not yet implemented in coreboot.
   To control fans, use software fan control methods in the meantime.

Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Felix Singer <[email protected]>

If BMP_LOGO is set, currently display_init_required() will always return
1, so that platform code will always initialize display. However, that
information isn't passed to vboot, which may result in unnecessary extra
reboots, for example when the payload needs to request display init (by
vb2api_need_reboot_for_display()).

Since there is already a Kconfig option VBOOT_ALWAYS_ENABLE_DISPLAY to
tell vboot that "display is available on this boot", enable it by
default if BMP_LOGO is set.

BUG=b:345085042
TEST=none
BRANCH=none

Change-Id: I20113ec464aa036d0498dedb50f0e82cb677ae93
Signed-off-by: Yu-Ping Wu <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83256
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Subrata Banik <[email protected]>
Reviewed-by: Julius Werner <[email protected]>

Fast boot will used pre-saved hardware configuration data to
accelerate the boot process, e.g. DDR training is skipped by using
pre-saved training data. Enable fast boot on cold and warm resets
by default.

Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590
Signed-off-by: Gang Chen <[email protected]>
Signed-off-by: Shuo Liu <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82080
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Lean Sheng Tan <[email protected]>

Before:
I2C0 - 401kHz
I2C4 - 405kHz

After:
I2C0 - 392kHz
I2C4 - 395kHz

HW: Change R8409/R8411 to 33ohm.

BUG=b:349743464,b:349735055
TEST=emerge-brox sys-boot/coreboot
     Test pass by EE

Change-Id: I985837b1b80e973f148529b446905580c0f95e98
Signed-off-by: Jian Tong <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290
Reviewed-by: Eric Lai <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Kun Liu <[email protected]>

Add RAM ID for
K3KL9L90CM-MGCT                 0 (0000)

BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=Run part_id_gen tool without any errors

Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f
Signed-off-by: Tony Huang <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300
Reviewed-by: Derek Huang <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>